During Static Random Access Memory (SRAM) semiconductor fabrication a conventional process for defining an implant into the substrate between thick field oxide regions for the storage cell region is depicted in FIGS. 5-8.
As shown in FIG. 5, wafer substrate 50 has been prepared with regions of thick (or field) oxide 51 and sacrificial oxide 52. Photoresist 53 is patterned to define a buried contact implant window 54. Once the implant window is prepared an implant is performed through window 54 that forms diffusion region 55. The edge of field oxide 51 was exposed during the implant which effectively changes the etch rate of the field oxide.
As shown in FIG. 6, photoresist 53 has been stripped as has sacrificial oxide 52. During the sacrificial oxide strip, thinning occurs at the exposed edge of field oxide 51 due to the change of the oxide's etch rate and thus results in the notched field oxide area 61.
Once the field oxide has been damaged by the buried contact implant and thinning occurs the cell area is now prone to leakage as demonstrated in FIG. 7. FIG. 7 shows a patterned portion of the cell with patterned polysilicon layer 71 making contact to diffusion region 72a. As can be seen, further thinning of field oxide 51 has occurred at notches 61 and 73. This thinning of field oxide reduces its ability to prevent cell leakage between diffusion 72a and diffusion 72b (as depicted by arrow 74 showing electron flow from one diffusion region to another).
As one skilled in the art recognizes, the cell leakage is very undesirable as the leakage will reduce the cell's storage capability and may even render the cell as totally defective.
The present invention provides an effective method that will avoid cell leakage while forming a low resistive path between a buried contact and a diffusion region.